Enhanced Bit Mapping for Digital Interface of a Wireless Communication Equipment in Multi-Time Slot and Multi-Mode Operation

ABSTRACT

A control device (CD) is dedicated to the control of the transmission of coded values onto a digital interface (I) connecting a baseband device (BBD) and a baseband interface device (BAI), comprising at least a modulator (M) feeding a gain controller (GC), of a wireless communication equipment. The control device (CD) comprises a storing means (MM 1 ) for storing a coding table establishing a correspondence between symbols for the baseband interface device (BAI) and coding values to transmit to this radiofrequency device through the digital interface (I). Tie coding table comprises a first group of symbols comprising data words for feeding the modulator (M) and a second group of symbols comprising command words for controlling the operation of the modulator (M) and/or the gain controller (GC). The control device (CD) also comprises a control means (CRM) arranged, when it receives a symbol from the baseband device (BBD), to determine in the storing means (MM  1 ) the coded value corresponding to this symbol in order it could be transmitted to the baseband interface device (BAI) through the digital interface (I).

The present invention relates to the digital baseband transmission pathof the wireless communication equipments, and more precisely to thecontrol of the modulator and/or the gain controller of such equipments,through a digital interface.

In certain communication networks, such as GSM (Global System for Mobilecommunications), it has been proposed to enhance the data rate throughnew standards, such as the so-called EGPRS standard (Enhanced GeneralPacket Radio Service). For instance the EGPRS standard has introduced inthe GSM network a new modulation scheme, named 8PSK (8 Phase ShiftKeying), to improve the data rate previously offered by the GMSK(Gaussian Minimum Shift Keying) modulation scheme.

For flexibility purpose of data transmission, the EGPRS standard definesa multi-time slot (or multislot) and multi-mode operation requiring thatmore than one time slot out of the eight time slots dividing a GSM framecould be used for data transmission with GMSK or 8PSK modulation. So,the EGPRS wireless communication equipments must comprise a modulatorable to switch easily from a GMSK modulation scheme to an 8PSKmodulation scheme and vice versa in consecutive time slots.

But, as it is known by one skilled in the art, GMSK is a constantenvelope modulation scheme which allows the use of a saturated poweramplification with high efficiency, while 8PSK is a modulation schemewhich delivers a modulated carrier that varies not only in phase butalso in amplitude and therefore can not allow the use of a saturatedpower amplification but for instance a linear one.

So, in multislot operation the modulation scheme changes but alsopossibly the power amplification mode, which unfortunately introducesinterferences between the adjacent channels associated to consecutivetime slots.

In order to reduce these interferences it has been proposed to ramp downthe transmit power by means of the gain controller of a power amplifierand to change the modulator and/or the power amplification mode during aguard period provided between the consecutive time slots. It is recalledthat the guard period is a time interval dedicated to control and/orswitching operation without data transmission.

An alternative to this solution has been notably described in the patentdocument WO 2004/021659. It consists of a joint GMSK/8PSK I/Q modulatoradapted to power ramping by means of I/Q signal shaping (where I and Qare respectively in-phase and quadrature components), without changingneither the power amplification mode nor the modulators. This is done byfeeding with zeros the joint GMSK/8PSK I/Q modulator, thereby allowingcontrol of the power of the I/Q signals.

If an external power control loop is used it is required that themodulator function be decoupled from the power control loop, or in otherwords that the ramping of the power amplifier be not determined by themodulator behaviour, but strictly by the power control loop. Thisstringent condition requires that the modulator output signal has aninstantaneous transition between on/off states (data mode versusforced-zero mode) rather than a smooth one. Such transitions requirethat the modulation switching as well as the gain changes be timedaccurately.

An industrial standard has been proposed to standardize the interfacesbetween the digital baseband processor (or device), the basebandinterface (or BAI) and the radiofrequency (RF) device (which isconnected to a power amplifier (or PA)).

It is recalled that, for the transmit direction, the digital basebandprocessor mainly comprises a digital signal processor (DSP) and acontroller device (e.g., ARM) interfacing to the BAI, the basebandinterface (or BAI) mainly comprises the modulator, a gain controller, adigital to analog converter (or DAC) and a postfilter interfacing to theradiofrequency (RF) device, and the RF device mainly comprises filters,gain stages and mixers. The digital baseband processor (or device), thebaseband interface (or BAI), the radiofrequency (RF) device and thepower amplifier (or PA) define what is named the transmission path of awireless communication equipments.

The digital baseband processor, the BAI and the RF device may be definedon a same chip, or on separate chips, and any combination of two ofthese three devices may be also defined on a same chip. So, they may beconnected one to the other in a “chip-to-chip connection mode” or in a“block-to-block connection mode” (when they are integrated on a samechip). But whatever the connection mode they need to be interfacedthrough a digital interface.

The industrial standard defines a digital interface, named “digital RFinterface” and capable of running a protocol named “digRF”, and acontrol device to facilitate the data transmission between the basebanddevice and the baseband interface (or BAI). This is done by means of acoding table stored in the control device and establishing acorrespondence between symbols for the radiofrequency device and codingvalues to transmit to this radiofrequency device through the digitalinterface.

For instance in the case of a GMSK/8PSK I/Q modulators the coding tablecomprises 16 symbols, two corresponding to data words for feeding theGMSK I/Q modulator, eight corresponding to data words for feeding the8PSK I/Q modulator, and the last six being reserved for proprietary use.

Some more information about the digital interface, the digRF protocoland the environment thereof may be found at the Internet address“www.digrf.com”, for instance in the document “DigRF, Baseband/RFdigital interface specification: Logical, Electrical and timingcharacteristics”, Version1.12.

This industrial standard is not yet sufficient. So, the object of thisinvention is to improve the situation.

For this purpose, it provides a control device, dedicated to the controlof the transmission of coded values onto a digital interface connectinga baseband device and a baseband interface device (or BAI device)(comprising at least a modulator feeding a gain controller), of awireless communication equipment, and comprising a storing means forstoring a coding table establishing a correspondence between symbols forthe BAI device and coding values to transmit to the BAI device throughthe digital interface.

This control device is characterized in that its coding table comprisesa first group of symbols comprising data words for feeding the modulatorand a second group of symbols comprising command words for controllingthe operation of the modulator and/or the gain controller, but also inthat it comprises a control means arranged, when it receives a symbolfrom the baseband device, to determine in the storing means the codedvalue corresponding to this symbol in order it could be transmitted tothe radiofrequency device through the digital interface.

In other words the invention offers to use some of the symbols, storedin the coding table, for feeding the modulator with data and theremaining symbols, also stored in the coding table, for the transmissionof commands to the modulator and/or the gain controller, through thedigital interface.

The control device according to the invention may include additionalcharacteristics considered separately or combined, and notably:

-   -   at least one of the symbols of the second group may be a command        word for assigning a chosen gain value to the gain controller,    -   at least one of the symbols of the second group may be a command        word for assigning a chosen working mode to a filter means        and/or a modulation means of the modulator,    -   at least one of the symbols of the second group may be a command        word for assigning a chosen working mode to a filter means        and/or a modulation means of the modulator and a chosen gain        value to the gain controller,    -   the working mode may be for instance an “initialization mode”        for pre-loading the filter means with a chosen sequence of        rotated valid symbols for an immediate up-ramping of the        modulator, or a “reset mode” to force binary values of zero into        the delay chain of the modulator's filter (to put all delays to        zero, resulting in a sharp transition to zero output, i.e. an        immediate down-ramping of the modulator), or else a “forced to        zero mode” to force at least one binary value of zero into the        modulator (which results in a smooth down ramping/up ramping at        the input). In this case, the control device may be arranged to        deliver a command word for assigning an initialization mode        before transmission to the filter means of a last guard bit        filling a guard interval, and/or to deliver a command word for        assigning a reset mode just after the transmission of an active        part of a data burst to the filter means and during the guard        interval,    -   when the modulator comprises a GMSK IQ modulator and a 8PSK I/Q        modulator, each coded value may be a four-bit word comprising        three most significant bits (MSB) and a low significant bit        (LSB) for differentiating the GMSK I/Q modulator from the 8PSK        I/Q modulator. In this case, the first group may comprise at        least eight symbols and the second group may comprise at least        six symbols.

The invention also provides a baseband device, for a wirelesscommunication equipment comprising a BAI device adapted to be connectedto said baseband device through a digital interface, and comprising acontrol device such as the one above introduced.

The invention also provides a baseband interface device (or BAI device)for a wireless communication equipment comprising a baseband device suchas the one above introduced and adapted to be connected to the BAIdevice through a digital interface. This BAI device comprises at least amodulator, a gain controller fed by the modulator, a storing meansadapted to store a control table establishing a correspondence betweencoding values, transmitted by the digital interface, and symbolsrepresenting command words for controlling its operation and data wordsfor feeding the modulator, and a control means connected to the digitalinterface, the modulator and the gain controller, and arranged, when itreceives a coding value from the digital interface, to determine in thestoring means the word corresponding to the received coding value inorder to transmit it to the modulator and/or the gain controller.

In alternative, the BAI device is dedicated to a wireless communicationequipment comprising a baseband device connected to it, through adigital interface, and a control device such as the one aboveintroduced.

It is important to notice that the baseband device, the BAI device andthe RF device may be defined on a same chip, or on separate chips, andthat any combination of two of these three devices may be also definedon a same chip. But whatever the configuration these devices must usethe above mentioned digital interface.

The invention also provides a wireless communication equipmentcomprising a baseband device, a digital interface, a control device suchas the one above introduced, a BAI device such as the one aboveintroduced, connected to the baseband device trough the digitalinterface, and a RF device connected to the BAI device.

In alternative, the wireless communication equipment may comprise abaseband device such as the one above introduced, a digital interface, aBAI device such as the one above introduced, connected to the basebanddevice through the digital interface, and a RF device connected to theBAI device.

Such equipments may be mobile phones, for instance.

Other features and advantages of the invention will become apparent onexamining the detailed specifications hereafter and the appendeddrawings, wherein:

FIG. 1 schematically illustrates an example of transmission pathcomprising a control device according to the invention,

FIG. 2A schematically illustrates a simplified example of embodiment ofa 8PSK I/Q modulator and a zeroth-order path of a linearized GMSK I/Qmodulator belonging to a joint 8PSK/GMSK I/Q modulator of acommunication device according to the invention,

FIG. 2B schematically illustrates a simplified example of embodiment ofthe first-order (or quadratic) path of the linearized GMSK I/Q modulatorbelonging to a joint 8PSK/GMSK I/Q modulator of a baseband interfacedevice according to the invention, and

FIG. 3 schematically illustrates a possible example of timing diagramsfor the linearized GMSK I/Q modulator of FIGS. 3A and 3B.

The appended drawings may not only serve to complete the invention, butalso to contribute to its definition, if need be.

As above mentioned and as it is schematically illustrated in FIG. 1 adigital baseband transmission path of a wireless communication equipmentcomprises a digital baseband processor (or device) BBD, and a basebandinterface device BAI, comprising at least a modulator M, a gaincontroller GC and a digital to analog converter DAC filter, connected tothe digital baseband device BBD through a digital interface I. Thedigital baseband transmission path is connected to the radiofrequency(RF) device RFD which is itself connected to a power amplifier PAconnected to an antenna AN. The digital baseband transmission path, theradiofrequency (RF) device RFD and the power amplifier PA constitute thetransmission path.

It is important to notice that the gain stage of the digital basebandtransmission path is usually distributed, one part comprising the gaincontroller GC being located inside the baseband interface device BAI (ina digital or analog form), and another part being located in the RFdevice RFD (in an analog form).

In the following description it will be considered that the digitalinterface I is of the type of the interface described in the above citeddocument “DigRF, Baseband/RF digital interface specification: Logical,Electrical and timing characteristics”, Version1.12. So, it will beconsidered in the following description, as an illustrating example,that the digital interface I is capable of running at least a part ofthe digRF protocol stack.

But the invention is not limited to this kind of digital interface.

Moreover, in the following description it will be considered (in a nonlimiting example of embodiment) that the baseband interface device BAIis a baseband and audio interface device.

Furthermore, in the following description it will be considered that themodulator M is a joint 8PSK/GMSK I/Q modulator installed in a wirelesscommunication equipment, such as a GSM mobile phone with enhanced datarate according to the EGPRS (or EDGE) standard. In other words themodulator M is adapted to switch in multimode operation from a GMSKmodulation scheme to an 8PSK modulation scheme and vice versa inconsecutive time slots of a GSM frame.

But the invention is not limited to this kind of switching whichrequires a switching between the linear and non-linear modes of a poweramplifier. Indeed this invention generally applies to any switchingschemes of modulators, and notably those based on Laurent's constructionof digitally phase modulated signals by superposition of amplitudemodulation pulses. Some more details about this Laurent's constructionmay be found in the document of P. A. Laurent “Exact and approximateconstruction of digital phase modulations by superposition of amplitudemodulated pulses (AMO)”, IEEE Transactions on communications, Vol. 42,N^(o). 2/3/4, 1994.

Furthermore, the invention is not limited to modulators installed inmobile phone. The modulator according to the invention may be installedin any wireless communication equipment, and notably in laptop or PDA(Personal Digital Assistant) comprising a communication device.

As it is known by one skilled in the art, the baseband device BBD of amobile phone (for instance) mainly comprises a speech coder, a channelcoder, an interleaver and a ciphering. This baseband device BBD islinked to the baseband and audio interface device BAI notably throughthe digital interface I (other connection means may be provided). Thebaseband and audio interface device BAI comprises a processing module PM(comprising a burst formatter (or builder), a differential encoder forGMSK signals, and a control module CTM), the joint 8PSK/GMSK I/Qmodulator M, the gain controller GC, and the digital to analog converterDAC.

As it is schematically illustrated in FIG. 1 the control module CTM maybe external to the modulator M, but it may also constitute a part of thejoint 8PSK/GMSK modulator M.

The control module CTM, the joint 8PSK/GMSK I/Q modulator M, the gaincontroller GC and the digital to analog converter DAC are preferablyintegrated circuits.

As illustrated in FIG. 1 the baseband device BBD may comprise at least apart of a control device CD for controlling the transmission of codedvalues to the modulator M through the digital interface I, which iscapable of running the digRF protocol stack (in this non limitingexample). This control device CD will be described below.

The modulator M is provided with digital input signals IS by theprocessing module PM and arranged, in the described example, to feedeither an 8PSK I/Q modulator M1 or a linearized GMSK I/Q modulator M2according to the type of the input signals IS to modulate. In FIG. 2, M1comprises MP1 and F0, M2 comprises M2 ₀ and M2 ₁, M2 ₀ comprises MP2 ₀and F0 (shared with M1), and M2 ₁ comprises MP2 ₁ and F1.

As illustrated in FIGS. 2A and 2B, the linearized GMSK I/Q modulator M2preferably comprises a zero-th order modulation path M2 ₀ (MP2 ₀ andF0), also named linear path, and at least a first order modulation pathM2 ₁ (MP2 ₁ and F1), also named quadratic path, fed with the same inputsignals IS. It is important to notice that the linearized GMSK I/Qmodulator M2 is more generally a n-th order GMSK I/Q modulator whichcomprises n+1 modulation paths (n≧0) fed with the same input signals IS.Therefore the modulator M may comprise a GMSK I/Q modulator comprisingmore than two modulation paths.

The linear path comprises a modulation part MP2 ₀ feeding a filter partF0, also named C0 filter. The quadratic path comprises a modulation partMP2 ₁ feeding a filter part F1, also named C1 filter.

The 8PSK I/Q modulator M1 comprises a modulation part MP1 feeding the C0filter F0 that it shares with the linear path of the linearized GMSK I/Qmodulator M2.

The respective outputs of the C0 filter F0 and C1 filter F1 areconnected to the inputs of a main combiner MC to feed it with modulatedand filtered I/Q signals. The output of the main combiner MC isconnected to the gain controller GC itself connected to the digital toanalog converter DAC to feed it with the modulated and filtered I/Qsignals OS.

The 8PSK I/Q modulator M1 and the linearized GMSK I/Q modulator M2 eachcomprise a modulation section for generating modulated digital I/Qsignals associated to time slots of GSM frames and a filter section forapplying a chosen pulse shape defined by filter values to the digitalI/Q signals in order to output modulated and filtered digital I/Qsignals.

As is schematically illustrated in FIG. 2A the modulation part MP1 ofthe multislot 8PSK F/Q modulator M1 may comprise a serial to parallelconverter SPC fed with serial data stream (or digital input signals) ISby the multiplexer MU of the modulator M. It is recalled that the speechsignals (but it may be also pure data) may be quantized by the speechcoder and then organized into data frames by the channel coder.

For instance the serial to parallel converter SPC is at least athree-bit serial to parallel converter that outputs three-bit parallelsignals. Preferably it is a four-bit serial to parallel converter thatoutputs four-bit parallel signals where the LSB (Least Significant Bit)is used to distinguish between GMSK data and 8PSK data as well asbetween various active (or gain)/reset/preload modes.

The modulation part MP1 of the multislot 8PSK I/Q modulator M1 alsocomprises a Grey mapper GM fed with the three-bit parallel signals andarranged to map each bit triplet on one out of eight complex signals.

The modulation part MP1 of the multislot 8PSK I/Q modulator M1 alsocomprises a complex multiplier CM0 arranged to shape the I/Q signalsoutputted by the Grey mapper GM. More precisely the complex multiplierCM0 is responsible for the mapping of the k-th symbols it receives ontothe unit circle. The complex multiplier CM0 multiplies each receivedsignal by a rotation signal equal to exp(jk3π/8) to introduce a rotationof 3kπ/8 radians.

The symbol mapping combines the signals outputted by the Grey mapper GMas well as the additional rotation symbol of the exp(j3πk/8) term. TheGrey mapper GM can be seen as a group of gates which translates the3-bit symbols into the corresponding position on a unit circle accordingto a chosen rule. So the multiplier CM0 outputted rotated symbols whichallow to avoid zero crossings in the RF envelope.

The modulation part MP1 of the multislot 8PSK I/Q modulator M1 alsocomprises a “shared” 3×1 multiplexer MX1 comprising a first input fed bythe output of the complex multiplier CM0, a second input for zerosetting, a third input fed by a complex multiplier CM1 of the modulationpart MP2 ₀, and one output feeding with input samples an up-sampler US1adapted to carry out an up-sampling aiming at inserting N-1 zeros aftereach input sample. For instance and as illustrated N=16.

The function of the multiplexer MX1 is to select between zeros duringeach guard period and the rotated 8PSK or GPSK symbols during the timeslots (or active part of the bursts). Feeding the up-sampler US1 (andthe following C0 filter F0) with zeros during the guard period enables asmooth step-on and step-off response of the C0 filter 0F.

This up-sampler US1 feeds the shared filter part (or C0 filter) F0 withzeros or modulated digital 8PSK or GMSK I/Q signals through amultiplexer MX2 ₀.

The serial to parallel converter SPC, the Grey mapper GM, the multiplierCM0, the shared multiplexer MX1 and the shared up-sampler US1 constitutethe modulation part MP1 of the multislot 8PSK I/Q modulator M1.

The C0 filter F0 is a pulse-shaping filter which has for instance 80taps C0 _(i) (i=0 to n, where n=79) and may be split into m sections F0_(s) (s=1 to m), where m=1 to 80, each having 80/m filter coefficientsC0 ₁ (for instance when m=5 there are 5 sections each having 16 taps).This C0 filter F0 is used for 8PSK and shared with the zeroth-order partof the GMSK modulator. It is recalled that in GSM, the time-bandwidthproduct is BT=0.3 and the Gaussian pulse is treated as limited to −2T .. . 2T.

The C0 pulse-shaping filter F0 is preferably a low pass filter defininga finite impulse response (FIR) filter. Such a low pass filter isdescribed in the document of P. Jung, “Laurent's representation ofbinary digital continuous phase modulated signals with modulation index½ revisited,” IEEE Trans. Comm., vol. 42, pp 221-224, 1994.

Each part F0 _(i) of the C0 pulse-shaping filter F0 applies a chosenpulse shape defined by filter values (or coefficients) C0 _(i)(t) to themodulated digital I/Q signals it receives in order to output modulatedand filtered digital I/Q signals. The signal serially travels throughall F0 _(i).

Each filter coefficient C0 _(i) of the C0 pulse-shaping filter F0 is fedwith the same signals (possibly time delayed) through a multiplexerMX2;. More precisely, the filter coefficient C0 ₀ is fed by the outputof the multiplexer MX2 ₀, which also feeds one of the three inputs ofthe following multiplexer MX2 ₁ through a module T₁. The filtercoefficient C0 ₁ is fed by the output of the multiplexer MX2 ₁, whichalso feeds one of the three inputs of the following multiplexer MX2 ₂through a module T₂, and so on. And finally, the filter coefficient C0_(n) is fed by the output of the multiplexer MX2 _(n) through a moduleT_(n). Each module T_(i) (i=1 to n) is arranged to introduce a chosendelay in time domain.

In the illustrated example, the C0 filter F0 also comprises n-1combiners (or adders) C1 to Cn for combining together the signalsrespectively outputted by each of its n filter coefficients C0 _(i). Sothe output of the last combiner (or adder) Cn of the C0 filter F0 isconnected to one of the two inputs of the main combiner MC, whose outputis connected to the gain controller GC, itself connected to the digitalto analog converter DAC.

The zero-th order modulation path (MP2 ₀ and F0) of the multislotlinearized GMSK I/Q modulator M2 comprises a mapper M0 arranged to mapeach received signals on one out of two complex signals.

The zero-th order modulation path also comprises a complex multiplierCM1 arranged to shape the I/Q signals outputted by the mapper M0. Thecomplex multiplier CM1 is responsible for the mapping of the symbols itreceives onto the unit circle (the mapper M0 outputs the possiblealphabet -1,1 and the complex multiplier CM1 maps the alphabet on theunit circle choosing one out of four possible positions). The complexmultiplier CM1 multiplies each received signal by a rotation signalequal to exp(jkπ/2) to introduce a rotation of kπ/2 radians.

The multiplier CM1 is connected to the third input of the abovementioned shared 3×1 multiplexer MX1.

The mapper M0, the multiplier CM1, the shared multiplexer MX1 and theshared up-sampler US1 constitute the modulation part MP2 ₀ of themultislot GMSK I/Q modulator M2.

The first order (or quadratic) modulation path (MP2, and F1) of themultislot linearized GMSK I/Q modulator M2 comprises a Finite StateMachine FSM fed with the same digital GMSK signals than the mapper M0 ofthe zero-th order modulation path (MP2 ₀ and F0).

The first order modulation path also comprises a mapper M1 arranged tomap each signal coming from the Finite State Machine FSM on one out oftwo complex signals.

The first order modulation path also comprises a complex multiplier CM2arranged to shape the I/Q signals outputted by the mapper M1. Thecomplex multiplier CM2 multiplies each received signal by a rotationsignal equal to exp(j(k-1)π/2) to introduce a rotation of (k-1)π/2radians.

The first order modulation path also comprises a 2×1 multiplexer MX3comprising one input fed by the output of the complex multiplier CM2,one input for zero setting and one output feeding with input samples anup-sampler US2 adapted to carry out an up-sampling aiming at insertingN-1 zeros after each input sample. For instance and as illustrated N=16.

The function of the multiplexer MX3 is to select between zeros duringeach guard period and the rotated GMSK symbols (or bits) during the timeslots (or active part of the bursts).

The Finite State Machine FSM, the mapper M1, the complex multiplier CM,the multiplexer MX3, and the up-sampler US2 defined together themodulation part MP2 ₁ of the first order modulation path of themultislot linearized GMSK I/Q modulator M2.

The up-sampler US2 feeds the filter part (or C1 filter) F1 with zeros ormodulated digital GMSK I/Q signals through a multiplexer MX4 ₀.

The C1 filter F1 is a pulse-shaping filter which has for instance 48taps C1 _(j) (j=0 to k, where k=47) and is split into p sections (F1_(p), where p=1 to 3 in this example), each having 16 filtercoefficients C1 _(j). The filter lengths of both filters F0 and F1 haveto be the same, namely 80 taps (so, k=n). However, the upper 32 taps ofthe C1 filter F1 are 0, so they do not have to be realized. It isimportant to notice that in order to insure a proper time alignment, thesummation between the output of the C0 filter F0 and C1 filter F1 has tobe done properly.

The C1 pulse-shaping filter F1 is preferably a low pass filter defininga finite impulse response (FIR) filter. Such a low pass filter is alsodescribed in the above mentioned document of P. Jung.

Each part F1 _(j) of the C1 pulse-shaping filter F1 applies a chosenpulse shape defined by filter values (or coefficients) C1 _(j)(t) to themodulated digital I/Q signals it receives in order to output modulatedand filtered digital I/Q signals.

Each coefficient filter C1 _(j) of the C1 pulse-shaping filter F1 is fedwith the same signals (or a delayed version of it) through a multiplexerMX4 _(j). More precisely, the filter coefficient C1 ₀ is fed by theoutput of the multiplexer MX4 ₀, which also feeds one of the threeinputs of the following multiplexer MX4 ₁ through a module T₁. Thefilter coefficient C1 ₁ is fed by the output of the multiplexer MX4 ₁,which also feeds one of the three inputs of the following multiplexerMX4 ₂ through a module T₂, and so on. And finally, the filtercoefficient C1 _(k1) is fed by the output of the multiplexer MX4 _(k)through a module T_(k).

In the illustrated example, the C1 filter F1 also comprises k-1combiners (or adders) C1 to Ck for combining together the signalsrespectively outputted by each of its k filter coefficients C1 _(j). Sothe output of the last combiner (or adder) Ck of the C1 filter F1 isconnected to one of the two inputs of the main combiner MC, whose outputis connected to the gain controller GC, itself connected to the digitalto analog converter DAC.

In the illustrated example the joint modulator M also comprisesinitialization (or pre-load) means for loading the FIR filter stateswith a “dummy” sequence of rotated valid symbols during the guard periodbetween two time slots, i.e. before the transmission of the active partof the burst (“initialization mode”), and/or just after the active partof a burst (“reset mode”). These rotated valid symbols are time-alignedwith the consecutive guard bits and data bits which respectively fillthe guard interval and the consecutive time slots that enclose it.

More precisely, the initialization operation aims at loading all theflip-flops in the C0 FIR filter F0 and C1 FIR filter F1 (modules T (fordelay in time domain)) with valid symbols.

A valid symbol is any possible bit combination out of the GMSK alphabetand properly rotated (and delayed).

The rotation of the dummy sequence allows to switch between a dummysequence and data bits without phase jumps. Effectively, the filter (F0,F1) having 80 taps, an input signal will have to travel first throughthe filter before being visible at the output. So, a valid dummysequence of rotated valid symbols must be loaded into the FIR filtersduring the guard period when it is possible to transmit anything as longas it is compliant with the power-time template.

With this kind of initialization one can obtain a sharp transition froma very small amplitude (due to the absence of transmission during theguard period) to the required amplitude level.

The initialization (or pre-load) means may be divided in two parts: afirst one MIa dedicated at least to the zeroth-order path (MP2 ₀ and F0)of the linearized GMSK I/Q modulator M2, and also possibly to themultislot 8PSK I/Q modulator M1 (as illustrated in FIG. 2A), and asecond one MIb dedicated to the multislot first-order path (MP2 ₁ andF1) of the linearized GMSK I/Q modulator M2 (as illustrated in FIG. 2B).

In the example illustrated in FIG. 2A, the first part MIa of theinitialization (or pre-load) means comprises a sub part MI0 dedicated tothe multislot 8PSK I/Q modulator M1 (and which is not mandatory whenGMSK switching is only used) and a second part MI1 dedicated to thezeroth-order path (MP2 ₀ and F0) of the linearized GMSK I/Q modulatorM2.

The first sub part MI0 comprises a serial to parallel converter SPC′ fedwith chosen sequence of initialization (or pre-load) bits PLS. As theserial to parallel converter SPC, this serial to parallel converter SPC′is for instance a three-bit serial to parallel converter that outputsthree-bit parallel signals PLS.

The first sub part MI0 also comprises a Grey mapper GM′ fed with thethree-bit parallel signals and arranged to map each bit triplet on oneout of eight complex signals.

The first sub part MI0 also comprises a complex multiplier CM0′ arrangedto shape the signals outputted by the Grey mapper GM′. The complexmultiplier CM0′ multiplies each received signal by a rotation signalequal to exp(jk3π/8) to introduce a rotation of 3kπ/8 radians. So themultiplier CM0′ outputs rotated symbols which allow to properlyphase-align them with the input data when switching between preload,reset and active modes.

In an alternative it is possible to generate input sequences in whichall the bits are equal to zero (0) or one (1). For this purpose it ispossible to hardwire the complex multiplier CM0′ input to minus one (−1)or one (1), thus omitting the serial to parallel converter SPC′ and alsothe Grey mapper (or even the whole branch if the 8PSK initializationswitching is not foreseen).

The second sub part MI1 comprises a mapper M0′ fed with a chosensequence of initialization (or pre-load) bits PLS′, and arranged to mapeach bit on one out of two complex signals as the mapper M0.

The second sub part MI1 also comprises a complex multiplier CM1′arranged to shape the signals outputted by the mapper M0′. The complexmultiplier CM1′ multiplies each received signal by a rotation signalequal to exp(jkπ/2) to introduce a rotation of kπ/2 radians. So themultiplier CM1′ outputs rotated symbols which allow to properlyphase-align them with the input data when switching between preload,reset and active modes.

In an alternative it is possible to generate input sequences in whichall the bits are equal to zero (0) or one (1). For this purpose it ispossible to hardwire the complex multiplier CM1′ input to minus one (−1)or one (1), thus omitting the mapper M0′.

The first part MIa of the initialization means also comprises a shared2×1 multiplexer MX0 comprising a first input fed by the output of thecomplex multiplier CM0′, a second input fed by the complex multiplierCM1′, and one output feeding with input samples an up-sampler US1′adapted to carry out an up-sampling aiming at inserting N-1 zeros aftereach input sample in order to output the chosen valid rotated bits forthe initialization (or pre-loading) mode. In the illustrated exampleN=16.

The function of the multiplexer MX0 is to select between the rotated8PSK and GPSK symbols during the pre-load or reset mode (when it isimplemented, i.e. when the initialization of the 8PSK path is foreseen).

The output of the up-sampler US1′ is connected to the first input of themultiplexer MX2 ₀ and to each first input of each other multiplexer MX2₁ to MX2 _(k) respectively through modules T′₁ to T′_(k) (delay in timedomain modules).

So the first input of each multiplexer MX2 _(i) is fed with rotatedsignals for initialization (or pre-load) mode purpose, the second inputof each multiplexer MX2 _(i) is fed with rotated signals for active modepurpose, and the third input of each multiplexer MX2 _(i) is fed withzeros sequence for a reset mode purpose.

The second part MIb of the initialization (or pre-load) means comprisesa Finite State Machine FSM preferably fed with the same chosen sequenceof initialization (or pre-load) bits PLS′ than the mapper M0′.

The second part MIb also comprises a mapper M1′ arranged to map eachsignal coming from the Finite State Machine FSM′ on one out of twocomplex signals.

The second part MIb also comprises a complex multiplier CM2′ arranged toshape the signals outputted by the mapper M1′. The complex multiplierCM2′ multiplies each received signal by a rotation signal equal toexpo(k-1)π/2) to introduce a rotation of (k-1)π/2 radians. So themultiplier CM2′ outputs rotated symbols which allow to properly phasealign them when switching between active, preload and reset modes.

The second part MIb also comprises an up-sampler US2′ fed by the outputof the multiplier CM2′ with the rotated symbol samples and adapted tocarry out an up-sampling aiming at inserting N- 1 zeros after eachsample in order to output the chosen valid rotated bits for theinitialization (or pre-loading) mode. In the illustrated example N=16.

The output of the up-sampler US2′ is connected to the first input of themultiplexer MX4 ₀ and to each first input of each other multiplexer MX4₁ to MX4 _(k) respectively through modules T′₁to T′_(k) (delay in timedomain modules).

So the first input of each multiplexer MX4 _(j) is fed with rotatedsignals for initialization (or pre-load) mode purpose, the second inputof each multiplexer MX4 _(j) is fed with rotated signals for active modepurpose, and the third input of each multiplexer MX4 _(j) is fed withzero sequence for a reset mode purpose.

In an alternative it is possible to generate input sequences in whichall the bits are equal to zero (0) or one (1). For this purpose it ispossible to hardwire the complex multiplier CM2′ input to minus one (−1)or one (1), thus omitting the mapper M2′ and the Finite State MachineFSM′.

One can notice that the complex multipliers CM1 and CM2 may comprise anadditional input fed with a chosen constant value and respectively withthe exp(jkπ/2and expo (k-1)π/2) terms, which results in the omission ofthe mappers M0 and M1. This is possible because the initialization (orpre-loading) needs to be done only with valid and properly rotatedsymbols. For this purpose it is possible to hardwire the additionalinput to 1 (or −1) and still rotating by the CMi's results in a properlyrotated dummy sequence which can be phase align with the active mode,i.e. switched without introducing phase jumps. In this case, it is alsopossible to omit the Finite State Machine FSM (which acts approximatelyas a modulo 2 adder) because it calculates the same output for everyconstant input.

The joint modulator M may also comprise reset means for loading the FIRfilter states with an all zero sequence (coefficients C0(i) and C1(j))just after the transmission of the active part of the burst and duringthe guard period. This chosen all zero sequence is provided to obtain afast transition of the FIR filter states from the last valid symbol(with the transmitted amplitude) to the all zero state of the guardperiod which corresponds to a very small amplitude. The zero sequencetravelling through the FIR filters appears as a smooth step-on/step-offat the filter's output.

Such an all zero sequence may be introduced through the third input ofeach multiplexer MX2 _(i) or MX4 _(j), or else through the first inputof each multiplexer MX2 _(i) or MX4 _(j) (dedicated to the pre-load (orinitialization) signals) when it is generated by the initializationmeans (in this case the initialization means also acts as a resetmeans).

As mentioned above, in order the transitions between on/off states (datamode versus initialization modes) be instantaneous, the modulationswitching as well as the gain changes must be timed accurately.

For this purpose the control device CD according to the inventioncomprises a dedicated memory MM1 in which is stored a coding tableestablishing a correspondence between symbols for the baseband and audiointerface device BAI and coding values to transmit to the radiofrequencydevice RFD through the digital interface I.

More precisely, this coding table comprises a first group of symbols(for instance at least 8 and preferably 10 (8 for 8PSK and 2 for GMSK))comprising data words for feeding the modulator M (M1, M2 ₀ and M2 ₁)and a second group of symbols (for instance at least 6) comprisingcommand words for controlling the operation of the modulator M and/orthe gain controller GC.

Such a coding table allows to convert a symbol, generated in thebaseband device BBD, into a specific coded value (or transmit symbolbits) adapted to be transmitted to the baseband and audio interfacedevice BAI through the digital interface I.

When the baseband device BBD needs to transmit data or command(s) to thebaseband and audio interface device BAI, it transmits it (or them) tothe control device CD. Then the control device CD transmits the data orcommand(s) to a control module CRM it comprises and which is arranged toaccess to the dedicated memory MM1 to determine in its coding table thecoded value corresponding to the data or command(s) to transmit. Thenthe control module CRM transmits this coded value to the baseband deviceBBD in order it could be transmitted to the baseband and audio interfacedevice BAI.

In the illustrated example the whole control device CD (control moduleCRM and dedicated memory MM1) is located inside the baseband device BBD,but this is not mandatory. Indeed, a part of the control device CD, andnotably the dedicated memory MM1, may be located outside the basebanddevice BBD.

The coding table may be implemented as a software or firmware, but itcould be also a protocol stack running on the digital interface I.

The processing module PM of the baseband and audio interface device BAIcomprises a dedicated memory MM2 storing a control table establishing acorrespondence between the coding values of the coding table and symbolsrepresenting command words for controlling the operation of themodulator M and/or the gain controller GC and data words for feeding themodulator M, and a control module CTM connected to the memory MM2, thedigital interface I, to receive the transmit symbol bits coded with thecoding table, and to the modulator M (and more precisely to themultiplexers MX1, MX2 _(i), MX3 and MX4 _(j) and also to MX0 when it isforeseen) and the gain controller GC.

When the control module CTM receives a coded value from the digitalinterface I, i.e. transmit symbol bits coded with the coding table, itaccesses to the dedicated memory MM2 to determine in its control tablethe word which corresponds to the received coded value. Then ittransmits this word to the modulator M and/or to the gain controller GC.

In the illustrated example the control module CTM and the dedicatedmemory MM2 are located inside the baseband and audio interface deviceBAI, but this is not mandatory. Indeed, at least the dedicated memoryMM2 may be located outside the baseband and audio interface device BAI.

The control table may be implemented as a software or firmware, but itcould be also a protocol stack running on the digital interface I. Thewhole modulator including the protocol stack could be also implementedin firmware.

The symbols of the second group may be used to define every type ofcommand adapted to control the operation of the modulator M and/or thegain controller GC.

For instance a command word may be provided for assigning a chosen gainvalue to the gain controller GC, or for assigning a chosen working modeto the C0 filter F0 (multiplexers MX2 _(i)) and/or the C1 filter F1(multiplexers MX4 _(j)) and/or the modulation part(s) MIa (multiplexersMX0 and MX1) and/or MIb (multiplexer MX3).

A command word may also be provided for assigning a chosen working modeto the C0 filter F0 (multiplexers MX2 _(i)) and/or the C1 filter F1(multiplexers MX4 _(j)) and/or the modulation part(s) MIa (multiplexersMX0 and MX1) and/or MIb (multiplexer MX3) and a chosen gain value to thegain controller GC.

Here one means by “working mode” the above described initialization modeused to pre-load the filter(s) F0 and/or F1 with a chosen sequence ofrotated valid symbols for an immediate up-ramping of the modulator M, orthe above described reset mode used to force binary values of zero intoall the delays of the modulator M for an immediate down-ramping of it,or else the transmission of valid data symbols out of the modulator'salphabet.

But other working modes may be envisaged.

When the modulator M or the gain controller GC receives a word from thecontrol module CTM, it transmits it to the concerned element(multiplexer and/or serial to parallel converter and/or mapper and/orFinite State Machine and/or gain multiplier) in order it could carry outthe corresponding action at the proper instant.

In case where the modulator M comprises a GMSK I/Q modulator M2 ₀ and M2₁ and a 8PSK I/Q modulator MI, the coding table and the control tableare preferably of the type defined in the above cited document “DigRF,Baseband/RF digital interface specification: Logical, Electrical andtiming characteristics”, Version1.12.

More precisely, each coded value according to the digRF standard is afour-bit word comprising three most significant bits (MSB) and a lowsignificant bit (LSB). The LSB is used to differentiate the GMSK I/Qmodulator M2 ₀ and M₁ from the 8PSK I/Q modulator M1. The MSB are sentfirst.

Moreover and still according to the digRF standard, the first group ofsymbols comprises ten symbols each dedicated to different data and thesecond group of symbols comprises six symbols dedicated to differentcommands.

An example of coding table is given hereafter (the control table can beeasily deduced from this coding table by inverting the input and theoutput):

Output (coded value) Output Input Hexadecimal (coded value) (symbol)value Binary value Description 0x0 0b0000 GMSK symbol “0” 0x2 0b0010GMSK symbol “1” 0x4 0b0100 Reset GMSK modulator (forced to zero) withoutgain change, symbol “R” 0x6 0b0110 Reset GMSK modulator (forced to zero)With gain change, symbol “RG” 0x8 0b1000 Pre-load GMSK modulator withoutgain change, symbol “P” 0xA 0b1010 Pre-load GMSK modulator With gainchange, symbol “PG” 0xC 0b1100 Zero without gain change, symbol “Z” 0xE0b1110 Zero with gain change, symbol “ZG” 0x1 0b0001 8PSK symbol “000”0x3 0b0011 8PSK symbol “001” 0x5 0b0101 8PSK symbol “010” 0x7 0b01118PSK symbol “011” 0x9 0b1001 8PSK symbol “100” 0xB 0b1011 8PSK symbol“101” 0xD 0b1101 8PSK symbol “110” 0xF 0b1111 8PSK symbol “111”

It is important to notice that the stored coding table or control tabledoes not need to comprise both hexadecimal values and binary values.

In this table the two first symbols are dedicated to the two differentdata words for the GMSK I/Q modulator M2 ₀ and M2 ₁, the six followingsymbols are initially dedicated to proprietary use and finally assignedto six modulator M (multiplexer configuration(s)) and/or gain controllerGC (gain change) commands, and the last eight symbols are dedicated tothe eight different data words for the 8PSK I/Q modulator M1.

Other formats of coded values may be envisaged.

According to the invention, it is now possible to use the proprietarybits i) to change gain(s) by means of digital multiplier(s) or analogscaling circuit(s), ii) to pre-load the FIR filters (F0 and F1) forstep-on of the regular I/Q pulse shaping filter, iii) to reset the FIRfilter for step-off of the regular I/Q pulse shaping filter, iv) and tocombine gain change(s) with pre-load, reset or forced to zero input.

The use of the command words (proprietary bits) is “meaningless” withoutan appropriate timing diagram defining the precise time at which eachcommand word must be transmitted to the modulator M and/or the gaincontroller GC in order it could carries out the corresponding action atthe proper instant.

A non limiting example of timing diagram, for the linearized GMSK I/Qmodulator M2 and more precisely for its multiplexers MX1 and MX3 (in theupper part) and for its multiplexers MX2 and MX4 (in the lower part), isillustrated in FIG. 3.

Here the pre-loading (or initialization) takes place after the fourleading guard bits referenced G1 to G4 which are followed by somespecially defined other guard bits G5 to G7. These guard bits filled theguard interval which is inserted between two consecutive time slotsfilled with data bits.

More precisely, in this example, the guard period takes G1, . . . , G7(guard bits) but the modulator M2 is switched on only after G4. So,during G1, G2 and G3 the multiplexers MX1 and MX3 are set to forced zero(second input on) while the multiplexers MX2 and MX4 are set to active(second input on). So, a smooth step-down from the previous GMSK burstis obtained. At G4, the multiplexers MX1 and MX3 are switched to GMSK(first input on) while the multiplexers MX2 and MX4 are set to pre-load(first input on) to enable the dummy sequence to be preloaded into theC0 or C1 filter. Thus, a fast amplitude transition occurs at the outputand new data bits follow the dummy sequence and “real data” reach theoutput after 2.5 symbols.

In FIG. 3 tail bits T0 to T2 are followed by data bits (not shown andcorresponding to a “normal” transmission), which are followed by othertail bits T′0 to T′2, and t/Tbits designates “normalized time scale”.

In this example, the resetting part (forced zero) follows after thethird trailing guard bit G′3, i.e. after the active part of the burstand after an additional transmission of three more specially definedguard bits (G′0 to G′2). The reset mode could be activated alreadyduring G′0 but in practice it is preferable to introduce some time forthe switch-off process.

The grey symbols in the upper part of FIG. 3 indicate that either onecan be chosen.

In this example only actions on the modulator's multiplexers have beenforeseen, but the resetting as well as the pre-loading may be combinedwith a gain change in the gain controller GC.

The invention is not limited to the embodiments of control device,baseband device, baseband (and audio) interface device and wirelesscommunication equipment described above, only as examples, but itencompasses all alternative embodiments which may be considered by oneskilled in the art within the scope of the claims hereafter.

Thus, in the preceding description it has been described a modulatorimplemented as an integrated circuit, but the invention also applies toa modulator implemented as a pure look-up table where all values arepre-calculated and stored or else as pure firmware.

1. Control device for controlling transmission of coded values onto adigital interface connecting a baseband device and a baseband interfacedevice comprising at least a modulator feeding a gain controller of awireless communication equipment, said control device comprising astoring means for storing a coding table establishing a correspondencebetween symbols for said baseband interface device and coding values totransmit to said baseband interface device through said digitalinterface characterized in that said coding table comprises a firstgroup of symbols comprising data words for feeding said modulator and asecond group of cymbols comprising command words for controlling theoperation of said modulator and/or said gain controller and that it alsocomprises a control means arranged, when it receives a symbol from thebaseband device to determine in said storing means the coded valuecorresponding to this symbol in order it could be transmitted to saidbaseband interface device through said digital interface.
 2. Controldevice according to claim 1, characterized in that at least one of thesymbols of said second group is a command word for assigning a chosengain value to said gain controller.
 3. Control device according to claim1, characterized in that at least one of the symbols of said secondgroup is a command word for assigning a chosen working mode to a filtermeans and/or a modulation means of said modulator.
 4. Control deviceaccording to claim 1, characterized in that at least one of the symbolsof said second group is a command word for assigning a chosen workingmode to a filter means and/or a modulation means of said modulator and achosen gain value to said gain controller.
 5. Control device accordingto claim 3, characterized in that said working mode is chosen in a groupcomprising at least an initialization mode to pre-load said filter meanswith a chosen sequence of rotated valid symbols for an immediateup-ramping of said modulator a reset mode to force binary values of zerointo said filter means of said modulator for an immediate down-rampingof said modulator and a forced to zero mode to force at least one binaryvalue of zero into said modulator.
 6. Control device according to claim5, characterized in that it is arranged to deliver a command word forassigning an initialization mode before transmission to said filtermeans of a last guard bit filling a guard interval.
 7. Control deviceaccording to claim 5, characterized in that it is arranged to deliver acommand word for assigning a reset mode just after the transmission ofan active part of a data burst to said filter means and during a guardinterval.
 8. Control device according to claim 1, wherein said modulatorcomprises a GMSK I/Q modulator and a 8PSK IQ modulator characterized inthat each coded value is a four-bit word comprising three mostsignificant bits and a low significant bit to differentiate said GMSKI/Q modulator and said 8PSK I/Q modulator.
 9. Control device accordingto claim 8, characterized in that said first group comprises at leasteight symbols and said second group comprises at least six symbols. 10.Baseband device for a wireless communication equipment comprising abaseband interface device adapted to be connected to said basebanddevice through a digital interface characterized in that it comprises acontrol device according to claim
 1. 11. Baseband interface device for awireless communication equipment comprising a baseband device accordingto claim 10, connected to it through a digital interface said basebandinterface device comprising at least a modulator and a gain controllerfed by said modulator characterized in that it comprises i) a storingmeans adapted to store a control table establishing a correspondencebetween coding values, transmitted by said digital interface and symbolsrepresenting command words for controlling its operation and data wordsfor feeding said modulator and ii) a control means connected to saiddigital interface modulator and gain controller and arranged, when itreceives a coding value from said digital interface to determine in saidstoring means the word corresponding to said received coding value inorder to transmit to said modulator and/or said gain controller. 12.Baseband interface device according to claim 11, characterized in thatit constitutes a baseband and audio interface device.
 13. Basebandinterface device for a wireless communication equipment comprising abaseband device connected to it through a digital interface and acontrol device according to claim 1, said baseband interface devicecomprising at least a modulator and a gain controller fed by saidmodulator characterized in that it comprises i) a storing means adaptedto store a control table establishing a correspondence between codingvalues, transmitted by said digital interface and symbols representingcommand words for controlling its operation and data words for feedingsaid modulator and ii) a control means connected to said digitalinterface modulator and gain controller and arranged when it receives acoding value from said digital interface to determine in said storingmeans the word corresponding to said received coding value in order totransmit it to said modulator and/or said gain controller.
 14. Basebandinterface device according to claim 13, characterized in that itconstitutes a baseband and audio interface device.
 15. Wirelesscommunication equipment comprising a baseband device and a digitalinterface characterized in that it comprises a control device accordingto claim 1, connected to said baseband device and a baseband interfacedevice, connected to said baseband device trough said digital interface.16. Wireless communication equipment, characterized in that it comprisesa baseband device according to claim 10, a baseband interface deviceaccording to, and a digital interface connecting said baseband device tosaid baseband interface device.